1. Field of the Invention
The present invention generally relates to analog-to-digital converters, and particularly to folding amplifiers in analog-to-digital converters.
2. Description of the Related Art
The analog-to-digital converter (ADC) is an important building block to interface the analog world to the digital world. Such ADC circuits have many applications that are widely used in such areas as digital telephone transmission, cell phones, medical imaging and wireless nodes, for example.
ADCs are found to have varying architectures, each of which typically may have a unique set of characteristics and limitations. Accordingly, a suitable analog-to-digital conversion technique should be utilized, depending on the particular application and the characteristics and limitations of the selected ADC. The most common types of ADCs are flash, successive approximation and sigma-delta, for example. The relatively fastest and conceptually simplest conversion process is the full flash or parallel flash ADC. A problem with such ADC circuit is that for N-bit resolution, it typically requires 2N−1 comparators and 2N resistors to generate reference voltages, which can lead to higher power consumption and larger silicon area.
Folding is a type of analog preprocessing that is used to produce more than one zero-crossing point. Folding is used to reduce the number of comparators, and thus, the power consumption and the silicon area of a flash ADC. The folding ADC is used to reduce the complexity of the flash ADC while substantially maintaining conversion speed. For (N=m+l) bits of resolution, for example, with m being the most significant bits and l being the least significant bits, the number of comparators required for the folding ADC is 2m−1 comparators for the MSBs and 2l−1 comparators for the LSBs. As such, the total number of comparators used in the folded ADC, (2m−1)+(2l−1), can be reduced to less than half of the number of comparators used in the flash ADC, which is 2N−1.
The applications of complementary metal-oxide-semiconductor (CMOS) current-mode circuits have increased dramatically due to deficiencies of their voltage-mode counterparts, such deficiencies including, for example, lack of suitability for low voltage design due to voltage swing problems. Existing voltage-mode folding amplifiers are typically built around differential pairs which generally are not suitable for low voltage design because of nonlinearity problems. Moreover, the input-output characteristic of a differential based folding amplifier can result in digitization errors. And, a problem with existing current-mode folding amplifier implementations is the degradation of the conversion accuracy, which may also result in digitization errors.
Thus, a CMOS current-mode folding amplifier that addresses the aforementioned problems is desired.